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d a t a sh eet product speci?cation supersedes data of 1999 sep 27 2003 dec 08 integrated circuits 74ahc573; 74ahct573 octal d-type transparent latch; 3-state
2003 dec 08 2 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 features esd protection: hbm eia/jesd22-a114-a exceeds 2000 v mm eia/jesd22-a115-a exceeds 200 v. balanced propagation delays all inputs have schmitt-trigger actions common 3-state output enable input functionally identical to the 74ahc/ahct563 and 74ahc/ahct373 inputs accepts voltages higher than v cc for ahc only: operates with cmos input levels for ahct only: operates with ttl input levels specified from - 40 to +85 c and - 40 to +125 c. description the 74ahc/ahct573 are high-speed si-gate cmos devices and are pin compatible with low power schottky ttl (lsttl). they are specified in compliance with jedec standard no. 7a. the 74ahc/ahct573 are octal d-type transparent latches featuring separate d-type inputs for each latch and 3-state outputs for bus oriented applications. a latch enable (le) input and an output enable ( oe) input are common to all latches. the 74ahc/ahct573 consists of eight d-type transparent latches with 3-state true outputs. when pin le is high, data at the dn inputs enters the latches. in this condition the latches are transparent, i.e. a latch output will change state each time its corresponding d-input changes. when pin le is low the latches store the information that was present at the d-inputs a set-up time preceding the high-to-low transition of le. when pin oe is low, the contents of the 8 latches are available at the outputs. when pin oe is high, the outputs go to the high-impedance off-state. operation of the oe input does not affect the state of the latches. the 74ahc/ahct573 is functionally identical to the 74ahc/ahct533, 74ahc/ahct563 and 74ahc/ahct373, but the 74ahc/ahct533 and 74ahc/ahct563 have inverted outputs and the 74ahc/ahct563 and 74ahc/ahct373 have a different pin arrangement. quick reference data gnd = 0 v; t amb =25 c; t r =t f 3.0 ns. notes 1. c pd is used to determine the dynamic power dissipation (p d in m w). p d =c pd v cc 2 f i n+ s (c l v cc 2 f o ) where: f i = input frequency in mhz; f o = output frequency in mhz; c l = output load capacitance in pf; v cc = supply voltage in volts; n = total load switching outputs; s (c l v cc 2 f o ) = sum of the outputs. 2. the condition is v i = gnd to v cc . symbol parameter conditions typical unit ahc ahct t phl /t plh propagation delay dn to qn; le to qn c l = 15 pf; v cc = 5 v 3.9 3.5 ns c i input capacitance v i =v cc or gnd 3.0 3.0 pf c o output capacitance 4.0 4.0 pf c pd power dissipation capacitance c l = 50 pf; f = 1 mhz; notes 1 and 2 12 18 pf
2003 dec 08 3 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 function table see note 1. note 1. h = high voltage level; h = high voltage level one set-up time prior to the high-to-low le transition; l = low voltage level; i = low voltage level one set-up time prior to the high-to-low le transition; z = high-impedance off-state. ordering information operating mode input internal latch output oe le dn q0 to q7 enable and read register (transparent mode) lhlll lhhhh latch and read register l l i l l llhhh latch register and disable outputs hl l lz hlhhz type number package pins package material code 74ahc573d 20 so20 plastic sot163-1 74ahct573d 20 so20 plastic sot163-1 74ahc573pw 20 tssop20 plastic sot360-1 74ahct573pw 20 tssop20 plastic sot360-1
2003 dec 08 4 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 pinning pin symbol description 1 oe 3-state output enable input (active low) 2 d0 data input 3 d1 data input 4 d2 data input 5 d3 data input 6 d4 data input 7 d5 data input 8 d6 data input 9 d7 data input 10 gnd ground (0 v) 11 le latch enable input (active high) 12 q7 3-state latch output 13 q6 3-state latch output 14 q5 3-state latch output 15 q4 3-state latch output 16 q3 3-state latch output 17 q2 3-state latch output 18 q1 3-state latch output 19 q0 3-state latch output 20 v cc supply voltage fig.1 pin configuration so20 and tsssop20. handbook, halfpage oe d0 d1 d2 d3 d4 d5 d6 d7 gnd v cc q0 q1 q2 q4 q5 q3 q6 q7 le 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 573 mna388 fig.2 logic symbol. handbook, halfpage mna389 d0 d1 d2 d3 d4 d5 d6 d7 oe le q0 q1 q2 q3 q4 q5 q6 q7 11 1 12 13 14 15 16 17 18 19 9 8 7 6 5 4 3 2 fi 3 l i di fig.3 iec logic symbol. handbook, halfpage mna390 12 13 14 15 16 17 18 11 c1 1 en 1d 19 9 8 7 6 5 4 3 2
2003 dec 08 5 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 fig.4 functional diagram. handbook, halfpage mna391 3-state outputs latch 1 to 8 q0 q1 q2 q3 q4 q5 q6 q7 12 13 14 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 le oe 9 11 1 8 7 6 5 4 3 2 mna392 q4 d4 q3 d3 q2 d2 q1 d1 q0 d0 d latch 1 q le le d latch 2 q d latch 3 q d latch 4 q d latch 5 q d latch 6 q d latch 7 q d latch 8 q oe le le le le le le le q5 d5 q6 d6 q7 d7 fig.5 logic diagram.
2003 dec 08 6 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 recommended operating conditions limiting values in accordance with the absolute maximum rating system (iec 60134); voltages are referenced to gnd (ground = 0 v). notes 1. the input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. for so20packages: above 70 c the value of p tot derates linearly with 8 mw/k. for tssop20 packages: above 60 c the value of p tot derates linearly with 5.5 mw/k. symbol parameter conditions 74ahc 74ahct unit min. typ. max. min. typ. max. v cc supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 v v i input voltage 0 - 5.5 0 - 5.5 v v o output voltage 0 - v cc 0 - v cc v t amb operating ambient temperature see dc and ac characteristics per device - 40 +25 +85 - 40 +25 +85 c - 40 +25 +125 - 40 +25 +125 c t r ,t f input rise and fall rates v cc = 3.3 v 0.3 v -- 100 --- ns/v v cc =5v 0.5 v -- 20 -- 20 ns/v symbol parameter conditions min. max. unit v cc supply voltage - 0.5 +7.0 v v i input voltage - 0.5 +7.0 v i ik input diode current v i < - 0.5 v; note 1 -- 20 ma i ok output diode current v o < - 0.5 v or v o >v cc + 0.5 v; note 1 - 20 ma i o output source or sink current - 0.5v 2003 dec 08 7 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 dc characteristics 74ahc type at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb =25 c v ih high-level input voltage 2.0 1.5 -- v 3.0 2.1 -- v 5.5 3.85 -- v v il low-level input voltage 2.0 -- 0.5 v 3.0 -- 0.9 v 5.5 -- 1.65 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 2.0 1.9 2.0 - v i o = - 50 m a 3.0 2.9 3.0 - v i o = - 50 m a 4.5 4.4 4.5 - v i o = - 4.0 ma 3.0 2.58 -- v i o = - 8.0 ma 4.5 3.94 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 2.0 - 0 0.1 v i o =50 m a 3.0 - 0 0.1 v i o =50 m a 4.5 - 0 0.1 v i o = 4.0 ma 3.0 -- 0.36 v i o = 8.0 ma 4.5 -- 0.36 v i li input leakage current v i =v cc or gnd 5.5 -- 0.1 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd 5.5 -- 0.25 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 5.5 -- 4.0 m a c i input capacitance -- 310pf
2003 dec 08 8 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 t amb = - 40 to +85 c v ih high-level input voltage 2.0 1.5 -- v 3.0 2.1 -- v 5.5 3.85 -- v v il low-level input voltage 2.0 -- 0.5 v 3.0 -- 0.9 v 5.5 -- 1.65 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 2.0 1.9 -- v i o = - 50 m a 3.0 2.9 -- v i o = - 50 m a 4.5 4.4 -- v i o = - 4.0 ma 3.0 2.48 -- v i o = - 8.0 ma 4.5 3.8 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 2.0 -- 0.1 v i o =50 m a 3.0 -- 0.1 v i o =50 m a 4.5 -- 0.1 v i o = 4.0 ma 3.0 -- 0.44 v i o = 8.0 ma 4.5 -- 0.44 v i li input leakage current v i =v cc or gnd 5.5 -- 1.0 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd 5.5 -- 2.5 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 5.5 -- 40 m a c i input capacitance --- 10 pf symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 dec 08 9 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 t amb = - 40 to +125 c v ih high-level input voltage 2.0 1.5 -- v 3.0 2.1 -- v 5.5 3.85 -- v v il low-level input voltage 2.0 -- 0.5 v 3.0 -- 0.9 v 5.5 -- 1.65 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 2.0 1.9 1.9 - v i o = - 50 m a 3.0 2.9 2.9 - v i o = - 50 m a 4.5 4.4 4.4 - v i o = - 4.0 ma 3.0 2.48 2.48 - v i o = - 8.0 ma 4.5 3.8 3.8 - v v ol low-level output voltage v i =v ih or v il i o =50 m a 2.0 --- v i o =50 m a 3.0 -- 0.1 v i o =50 m a 4.5 -- 0.1 v i o = 4.0 ma 3.0 -- 0.1 v i o = 8.0 ma 4.5 -- 0.44 v i li input leakage current v i =v cc or gnd 5.5 -- 2.0 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd 5.5 -- 10.0 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 5.5 -- 80 m a c i input capacitance --- 10 pf symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 dec 08 10 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 74ahct type at recommended operating conditions; voltages are referenced to gnd (ground = 0 v). symbol parameter test conditions min. typ. max. unit other v cc (v) t amb =25 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 4.5 4.4 4.5 - v i o = - 8.0 ma 4.5 3.94 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 4.5 - 0 0.1 v i o = 8.0 ma 4.5 -- 0.36 v i li input leakage current v i =v ih or v il 5.5 -- 0.1 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o =0 5.5 -- 0.25 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 5.5 -- 4.0 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o =0 4.5 to 5.5 -- 1.35 ma c i input capacitance -- 310pf t amb = - 40 to +85 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 4.5 4.4 -- v i o = - 8.0 ma 4.5 3.8 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 4.5 -- 0.1 v i o = 8.0 ma 4.5 -- 0.44 v i li input leakage current v i =v ih or v il 5.5 -- 1.0 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o =0 5.5 -- 2.5 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 5.5 -- 40 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o =0 4.5 to 5.5 -- 1.5 ma c i input capacitance --- 10 pf
2003 dec 08 11 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 t amb = - 40 to +125 c v ih high-level input voltage 4.5 to 5.5 2.0 -- v v il low-level input voltage 4.5 to 5.5 -- 0.8 v v oh high-level output voltage v i =v ih or v il i o = - 50 m a 4.5 4.4 -- v i o = - 8.0 ma 4.5 3.70 -- v v ol low-level output voltage v i =v ih or v il i o =50 m a 4.5 -- 0.1 v i o = 8.0 ma 4.5 -- 0.55 v i li input leakage current v i =v ih or v il 5.5 -- 2.0 m a i oz 3-state output off current v i =v ih or v il ; v o =v cc or gnd per input pin; other inputs at v cc or gnd; i o =0 5.5 -- 10.0 m a i cc quiescent supply current v i =v cc or gnd; i o = 0 5.5 -- 80 m a d i cc additional quiescent supply current per input pin v i =v cc - 2.1 v; other inputs at v cc or gnd; i o =0 4.5 to 5.5 -- 1.5 ma c i input capacitance --- 10 pf symbol parameter test conditions min. typ. max. unit other v cc (v)
2003 dec 08 12 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 ac characteristics 74ahc573 gnd = 0 v; t r =t f 3.0 ns. symbol parameter test conditions min. typ. max. unit waveforms c l (pf) v cc = 3.0 to 3.6 v t amb =25 c; note 1 t phl /t plh propagation delay dn to qn see figs 6 and 10 15 - 5.5 11.0 ns propagation delay le to qn see figs 7 and 10 15 - 5.8 11.9 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 - 5.8 11.5 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 - 6.8 11.0 ns t phl /t plh propagation delay dn to qn see figs 6 and 10 50 - 7.8 14.5 ns propagation delay le to qn see figs 7 and 10 50 - 8.3 15.4 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 - 8.3 15.0 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 - 9.7 14.5 ns t w enable pulse width high see figs 7 and 10 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns t amb = - 40 to +85 c t phl /t plh propagation delay dn to qn see figs 6 and 10 15 1.0 - 13.0 ns propagation delay le to qn see figs 7 and 10 15 1.0 - 14.0 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 1.0 - 13.5 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 1.0 - 13.0 ns t phl /t plh propagation delay dn to qn see figs 6 and 10 50 1.0 - 16.5 ns propagation delay le to qn see figs 7 and 10 50 1.0 - 17.5 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 1.0 - 17.0 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 1.0 - 16.5 ns t w enable pulse width high see figs 7 and 10 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns
2003 dec 08 13 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 t amb = - 40 to +125 c t phl /t plh propagation delay dn to qn see figs 6 and 10 15 1.0 - 14.0 ns propagation delay le to qn see figs 7 and 10 15 1.0 - 15.0 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 1.0 - 14.5 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 1.0 - 14.0 ns t phl /t plh propagation delay dn to qn see figs 6 and 10 50 1.0 - 18.5 ns propagation delay le to qn see figs 7 and 10 50 1.0 - 19.5 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 1.0 - 19.0 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 1.0 - 18.5 ns t w enable pulse width high see figs 7 and 10 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns v cc = 4.5 to 5.5 v t amb =25 c; note 2 t phl /t plh propagation delay dn to qn see figs 6 and 10 15 - 3.9 6.8 ns propagation delay le to qn see figs 7 and 10 15 - 4.2 7.7 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 - 4.4 7.7 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 - 4.6 7.7 ns t phl /t plh propagation delay dn to qn see figs 6 and 10 50 - 5.5 8.8 ns propagation delay le to qn see figs 7 and 10 50 - 5.9 9.7 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 - 6.3 9.7 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 - 7.4 9.7 ns t w enable pulse width high see figs 7 and 10 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns t amb = - 40 to +85 c t phl /t plh propagation delay dn to qn see figs 6 and 10 15 1.0 - 8.0 ns propagation delay le to qn see figs 7 and 10 15 1.0 - 9.0 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 1.0 - 9.0 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 1.0 - 9.0 ns t phl /t plh propagation delay dn to qn see figs 6 and 10 50 1.0 - 10.0 ns propagation delay le to qn see figs 7 and 10 50 1.0 - 11.0 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 1.0 - 11.0 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 1.0 - 11.0 ns t w enable pulse width high see figs 7 and 10 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns symbol parameter test conditions min. typ. max. unit waveforms c l (pf)
2003 dec 08 14 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 notes 1. typical values at v cc = 3.3 v. 2. typical values at v cc = 5.0 v. t amb = - 40 to +125 c t phl /t plh propagation delay dn to qn see figs 6 and 10 15 1.0 - 8.5 ns propagation delay le to qn see figs 7 and 10 15 1.0 - 10.0 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 1.0 - 10.0 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 1.0 - 10.0 ns t phl /t plh propagation delay dn to qn2 see figs 6 and 10 50 1.0 - 11.0 ns propagation delay le to qn see figs 7 and 10 50 1.0 - 12.5 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 1.0 - 12.5 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 1.0 - 12.5 ns t w enable pulse width high see figs 7 and 10 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns symbol parameter test conditions min. typ. max. unit waveforms c l (pf)
2003 dec 08 15 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 74ahct573 gnd = 0 v; t r =t f 3.0 ns. symbol parameter test conditions min. typ. max. unit waveforms c l (pf) v cc = 4.5 to 5.5 v; note 1 t amb =25 c t phl /t plh propagation delay dn to qn see figs 6 and 10 15 - 3.5 5.5 ns propagation delay le to qn see figs 7 and 10 15 - 3.9 6.0 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 - 4.1 6.5 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 - 4.5 6.5 ns t phl /t plh propagation delay dn to qn see figs 6 and 10 50 - 4.9 7.5 ns propagation delay le to qn see figs 7 and 10 50 - 5.5 8.5 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 - 5.9 8.5 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 - 6.4 9.0 ns t w enable pulse width high see figs 7 and 9 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns t amb = - 40 to +85 c t phl /t plh propagation delay dn to qn see figs 6 and 10 15 1 - 6.5 ns propagation delay le to qn see figs 7 and 10 15 1 - 7.0 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 1 - 7.5 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 1 - 7.5 ns t phl /t plh propagation delay dn to qn see figs 6 and 10 50 1 - 8.5 ns propagation delay le to qn see figs 7 and 10 50 1 - 9.5 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 1 - 10.0 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 1 - 10.0 ns t w enable pulse width high see figs 7 and 9 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns
2003 dec 08 16 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 note 1. typical values at v cc = 5.0 v. t amb = - 40 to +125 c t phl /t plh propagation delay dn to qn see figs 6 and 10 15 1 - 7.0 ns propagation delay le to qn see figs 7 and 10 15 1 - 7.5 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 15 1 - 8.5 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 15 1 - 8.5 ns t phl /t plh propagation delay don to qn see figs 6 and 10 50 1 - 9.5 ns propagation delay le to qn see figs 7 and 10 50 1 - 11.0 ns t pzh /t pzl propagation delay oe to qn see figs 9 and 10 50 1 - 11.0 ns t phz /t plz propagation delay oe to qn see figs 9 and 10 50 1 - 11.5 ns t w enable pulse width high see figs 7 and 9 50 5.0 -- ns t su set-up time dn to le see fig.8 50 3.5 -- ns t h hold time dn to le see fig.8 50 1.5 -- ns symbol parameter test conditions min. typ. max. unit waveforms c l (pf)
2003 dec 08 17 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 ac waveforms fig.6 the data input (dn) to output (qn) propagation delays. handbook, halfpage mna811 dn input qn output t phl t plh gnd v i v m v m v oh v ol family v i input requirements v m input v m output ahc gnd to v cc 50% v cc 50% v cc ahct gnd to 3.0 v 1.5 v 50% v cc fig.7 the latch enable input (le) pulse width, the latch enable input to output (qn) propagation delays. handbook, full pagewidth mna812 le input qn output t phl t plh t w 1/f max v m v oh v i gnd v ol v m family v i input requirements v m input v m output ahc gnd to v cc 50% v cc 50% v cc ahct gnd to 3.0 v 1.5 v 50% v cc
2003 dec 08 18 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 fig.8 data set-up and hold times for the dn input to the le input. family v i input requirements v m input ahc gnd to v cc 50% v cc ahct gnd to 3.0 v 1.5 v handbook, full pagewidth mna814 t h t su t h t su v m v m v i gnd v i gnd le input dn input the shaded areas indicate when the input is permitted to change for predictable output performance. fig.9 the 3-state enable and disable times. handbook, full pagewidth mna450 t plz t phz outputs disabled outputs enabled v oh - 0.3 v v ol + 0.3 v outputs enabled output low-to-off off-to-low output high-to-off off-to-high oe input v i v cc v m (1) v ol v oh gnd gnd t pzl t pzh v m (2) v m (2) family v i input requirements v m (1) input v m (2) output ahc gnd to v cc 50% v cc 50% v cc ahct gnd to 3.0 v 1.5 v 50% v cc
2003 dec 08 19 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 fig.10 load circuitry for switching times. test s1 t plh /t phl open t plz /t pzl v cc t phz /t pzh gnd handbook, full pagewidth open gnd v cc v cc v i v o mna183 d.u.t. c l r t r l = 1 k w pulse generator s1 definitions for test circuit: r l = load resistor. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to the output impedance z o of the pulse generator.
2003 dec 08 20 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 package outlines unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec jeita mm inches 2.65 0.3 0.1 2.45 2.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.1 0.4 sot163-1 10 20 w m b p detail x z e 11 1 d y 0.25 075e04 ms-013 pin 1 index 0.1 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.51 0.49 0.30 0.29 0.05 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale x q a a 1 a 2 h e l p q e c l v m a (a ) 3 a so20: plastic small outline package; 20 leads; body width 7.5 mm sot163-1 99-12-27 03-02-19
2003 dec 08 21 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.5 0.2 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot360-1 mo-153 99-12-27 03-02-19 w m b p d z e 0.25 110 20 11 pin 1 index q a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm sot360-1 a max. 1.1
2003 dec 08 22 philips semiconductors product speci?cation octal d-type transparent latch; 3-state 74ahc573; 74ahct573 data sheet status notes 1. please consult the most recently issued data sheet before initiating or completing a design. 2. the product status of the device(s) described in this data sheet may have changed since this data sheet was published. the latest information is available on the internet at url http://www.semiconductors.philips.com. 3. for data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. level data sheet status (1) product status (2)(3) definition i objective data development this data sheet contains data from the objective speci?cation for product development. philips semiconductors reserves the right to change the speci?cation in any manner without notice. ii preliminary data quali?cation this data sheet contains data from the preliminary speci?cation. supplementary data will be published at a later date. philips semiconductors reserves the right to change the speci?cation without notice, in order to improve the design and supply the best possible product. iii product data production this data sheet contains data from the product speci?cation. philips semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. relevant changes will be communicated via a customer product/process change noti?cation (cpcn). definitions short-form specification ? the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition ? limiting values given are in accordance with the absolute maximum rating system (iec 60134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information ? applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support applications ? these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes ? philips semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. when the product is in full production (status production), relevant changes will be communicated via a customer product/process change notification (cpcn). philips semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
? koninklijke philips electronics n.v. 2003 sca75 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. philips semiconductors C a worldwide company contact information for additional information please visit http://www.semiconductors.philips.com . fax: +31 40 27 24825 for sales of?ces addresses send e-mail to: sales.addresses@www.semiconductors.philips.com . printed in the netherlands r44/02/pp 23 date of release: 2003 dec 08 document order number: 9397 750 12156

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